LattePanda + FPGA: Create a Custom UART Over PCIe with Python Access

by L.P.

Leveraging LattePanda as a compact x86 Linux host, this implementation demonstrates direct PCIe communication with a Xilinx FPGA integrating a UARTLite core. The FPGA exposes a standard TTY interface under Linux, enabling user-space applications—such as Python scripts—to exchange data over PCIe without kernel-level driver development. This approach provides a robust, low-latency pipeline for embedded systems requiring FPGA acceleration or custom peripherals.

Hardware and Software Components

Hardware

FPGA: Xilinx Artix-7 (XC7A200T)
RF Transceiver: Analog Devices AD9361 (70 MHz - 6 GHz)
GPS Module: SIM68 (NMEA 0183 Output)
DDR Memory: MT41K256M16HA-125 AAT
Host Board: LattePanda Sigma
Interface: PCle Gen1 x4 (10 Gbps via M.2 connector)
Data Path: XDMA over AXl bus
UART Peripheral: AXI UARTLite lP Core (9600 baud)
Form Factor: M.2 2280(80mm x22mm)

Software

AMD Vivado Design Suite

The Making Process

For complete project details, example code, and step-by-step instructions, please visit Hackster: UARTLite FPGA to Linux: TTY Driver + Python Access via PCIe

Why choose LattePanda Sigma

LattePanda Sigma’s powerful PCIe support and Linux compatibility make it ideal for integrating FPGA projects like UARTLite communication. Its compact x86 platform gives you the flexibility and performance for advanced hardware-software solutions—all with easy development and strong community support.

Conclusion

This project showcases a practical implementation of UARTLite over PCIe, combining FPGA logic with a Linux TTY driver for transparent serial communication. By exposing the UART interface as a standard device node, it enables efficient, low-latency data exchange and convenient access via Python or other user-space applications. This approach provides a solid foundation for designing high-performance custom peripherals that integrate seamlessly into Linux environments.