Carrier Board Power Up sequence

I need to design a carrier board for the latte panda MU.

But there is missing information about the Power Up sequence.
When designing a carrier board, the supply are activated by the PSON signal.(SLS_S0 on the MU SOM ).

Depending on the complexity of the carrier, there could be multiple dc/dc and LDO involved in the power up sequence.

Usually, there is a power good indicator that goes back to the Module to indicate that the Power is good and stable. 

Since the MU module does not have the PowerGood Signal, It must be based on a certain amount of time . How much time do we have to make all power stable after the assertion of the PSON signal?